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WIS GO7007 Single-Chip Streaming Media Encoder
The GO7007 is a monolithic multi-format video compression chip. This high-performance chip uses multiple algorithms to buffer and compress raw video data into video streams. The output video stream is a versatile GoStreamTM format that can easily be transcoded by external processors into MPEG-1, MPEG-2, MPEG-4, and H.263 formats. The video streams are output through a Host Parallel Interface (HPI) or a Universal Serial Bus (USB) interface. The GO7007 is capable of delivering streaming video up to full-D1 resolution at a full-motion frame rate, over the Web and emerging broadband networks. It is ideal for a wide range of encoding applications, from DVRs/PVRs to PC/Web cameras. Optimizing Encoding Performance WIS Technologies' unique encoder architecture provides flexibility to accommodate many different ISO/ITU video standards. The ability to output video streams in almost any standard format greatly benefits upgrade flexibility as standards evolve. Enabling application-level conference bridging and legacy video streaming are additional benefits of the WIS GO7007. WIS GO chip integration enables a glueless logic interface between the GO7007 and the CMOS image sensors. Included on the chip are SDRAM and USB controllers and I2C and HPI interfaces. Full resolution can be achieved with 4MB PC100 SDRAM to reduce system costs.
The WIS GO7007 is a real-time MPEG-4 video compression chip. This high performance encoder enables developers to create and deliver streaming video over the Web, emerging broadband, and mobile networks.
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Advanced Features:
Output Formats MPEG-4 Simple Profile @ L3 plus B-frame support; DivX and WISmp4 compatible MPEG-2 MP @ ML MPEG-1, H.263, MJPEG User-defined formats Video Input CCIR-601 and CCIR-656 YUV (8-bit) 4:2:2 progressive or interlace; all four types of RGB Bayer Maximum input size: NTSC interlaced: 720 x 480 @ 30fps or 720 x 240 @ 60fps PAL: 720 x 576 @ 25fps or 720 x 288 @ 50fps Resolution from 64 x 64 to 720 x 576 (16pixel increments) Frame rate up to 30fps (full-D1) or 120fps (CIF) WIS-patented RGB Bayer to YUV conversion (high quality) WIS-patented de-interlace and 4:2:2 to 4:2:0 conversion Optional 1:2 horizontal, vertical, or bi-directional scaling Programmable median, low-pass and edge enhancement filtering (up to 10 run-time . adjustable parameters)
Video Compression WIS-patented Motion Estimation Engine (search range +/-127 horizontal PEL and +/63 vertical PEL with half-PEL accuracy) WIS-patented high precision DCT/IDCT and (de)quantize Advanced scene change detection and GOP adjusting 48MHz to 96MHz (depending on resolution) Programmable GOP structures of I, IP, IBP, IBBP WIS-patented advanced MPEG-4 bit-rate control (CBR/VBR) from 1Kbps to 40Mbps Video Quality and Features DVD quality full-D1 video at 2Mbps High quality 40Kbps QCIF video for low bandwidth communication 2-hour 640 x 352 movie in one 650M CD (average PSNR about 40db) Dynamically adjustable bit rate and frame rate to fit variable bandwidths (for Internet communication applications) Drivers, SDK, related software (decoding/ transcoding, post-process, Internet-ready software) and sample applications provided Most features and parameters are configurable from host (e.g., PC) side Internal algorithms of scene change and bitrate control are upgradeable
The WIS GO7007 meets the demand for versatility in a broad range of video applications. PAGE 2
Design for Test Full scan methodology Specifications 208-pin PQFP (28mm x 28mm) 3.3V, 0.18mm, 5-layer metal, single poly 4MB or 8MB 32-bit PC100 external SDRAM USB1.1 and 16-bit parallel I/F Power consumption: 350mW
System-on-Chip Design of the WIS GO7007 Encoder. Note that most of the blocks are interconnected over a common bus, simplifying the design and encouraging reusability of the intellectual property.
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Pin Assignment (top view)
Figure 0-1 GO7007 Pin Diagram
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Table 0-1 Pin List
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Pin Name AVDD_MPLL VSS_MPLL AVDD_MPLL VSS_MPLL VSS_MPLL DVDD_MPLL USB_EN MPLL_BP UPLL_BP TEST_EN SCAN_EN BOOT_SEL VDD_IO VSS_IO XP_INT0/TDI CBUS_IORDY/TCK INT_ACK/MON_EN RET_INT/TDO VDD_CORE VSS_CORE CBUS_WE/TMS CBUS_ALE/TRST CBUS_AD15 CBUS_AD14 CBUS_AD13 CBUS_AD12 CBUS_AD11 VDD_IO VSS_IO CBUS_AD10 CBUS_AD9 VDD_CORE VSS_CORE AD2 AD3 AD4 AD5 Pin # 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Pin Name VDD_IO SDRAM_DQ2 SDRAM_DQ1 SDRAM_DQ0 SDRAM_DQ15 VSS_IO VDD_CORE VSS_CORE VDD_IO SDRAM_DQ14 SDRAM_DQ13 SDRAM_DQ12 SDRAM_DQ11 VSS_IO VDD_IO SDRAM_DQ10 SDRAM_DQ9 SDRAM_DQ8 SDRAM_CLK VDD_CORE VSS_CORE VSS_IO VDD_IO SDRAM_CLK_LB SDRAM_A9 SDRAM_A8 SDRAM_A7 VSS_IO VDD_IO SDRAM_A6 SDRAM_A5 SDRAM_A4 VDD_CORE VSS_CORE SDRAM_A3 VSS_IO VDD_IO Pin # 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 Pin Name SDRAM_DQ22 SDRAM_DQ21 VSS_IO VDD_IO SDRAM_DQ20 SDRAM_DQ19 VDD_CORE VSS_CORE SDRAM_DQ18 VSS_IO VDD_IO SDRAM_DQ17 SDRAM_DQ16 SDRAM_A2 SDRAM_A1 VSS_IO VDD_IO SDRAM_A0 SDRAM_A10 VDD_CORE VSS_CORE SDRAM_BA1 VSS_IO VDD_IO SDRAM_BA0 SDRAM_CS# SDRAM_RAS# SDRAM_CAS# VSS_IO VDD_IO SDRAM_WE# SDRAM_DQM VDD_CORE VSS_CORE SUSPEND_LB SUSPEND VDD_USB Pin # 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 Pin Name VREF PCLK VSS_IO VDD_IO AD0 AD1 VDD_CORE VSS_CORE CBUS_AD8 CBUS_AD7 CBUS_AD6 CBUS_AD5 CBUS_AD4 CBUS_AD3 CBUS_AD2 CBUS_AD1 CBUS_AD0 VSS_IO VDD_IO VDD_CORE VSS_CORE AD11 AD12 AD13 AD14 AD15 WR# RD# ALE INT GPIO0 GPIO1 VDD_CORE VSS_CORE GPIO2 GPIO3 VSS_IO
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38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
AD6 AD7 AD8 AD9 AD10 VSS_IO VDD_IO SDRAM_DQ7 VDD_CORE VSS_CORE SDRAM_DQ6 SDRAM_DQ5 SDRAM_DQ4 SDRAM_DQ3 VSS_IO
90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
SDRAM_DQ31 SDRAM_DQ30 SDRAM_DQ29 SDRAM_DQ28 VSS_IO VDD_IO SDRAM_DQ27 SDRAM_DQ26 VDD_CORE VSS_CORE SDRAM_DQ25 VSS_IO VDD_IO SDRAM_DQ24 SDRAM_DQ23
142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
USB+ USBVSS_USB USB_CLK PDATA0 PDATA1 PDATA2 PDATA3 VDD_CORE VSS_CORE PDATA4 PDATA5 PDATA6 PDATA7 HREF
194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
VDD_IO MXI MXO SYNC_HPI DBG_INT MCLK USBRST_EN RESET# VDD_CORE VSS_CORE DEBUG_MODE BIST_FAIL BIST_DONE BIST_RESET BIST_RUN
Table 0-2 Pin Description
Symbol PLL Pins AVDD_MPLL VSS_MPLL DVDD_MPLL MPLL_BP 1, 3 2, 4, 5 6 8 Pin # Pin Type Supply Supply Supply Input Description 1.8V Analog power supply for Master clock PLL Ground for Master clock PLL 1.8V Digital power supply for Master clock PLL Master clock PLL Bypass. When pin is tied to ground, master clock is generated by internal PLL locked to MXI. Otherwise, MCLK is used as master clock input. USB clock PLL Bypass. When pin is tied to ground, USB clock is generated by internal PLL locked to MXI. Otherwise, USB_CLK is used as USB clock input. Oscillator Input Usually connected to the crystal Use this Master Clock input pin when Master clock PLL is bypassed. Test Enable. Reserved for manufacturers' use. Connect pin to ground under normal operation. Note
UPLL_BP
9
Input
1
MXI MXO MCLK Built-In Self Test Pins TEST_EN
195 196 199
Input Output Input
10
Input
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SCAN_EN
11
Input
Scan Enable. Reserved for manufacturers' use. Connect pin to ground under normal operation. Built-In Self Test Fail indicator Built-In Self Test Done indicator Built-In Self Test Reset. Reserved for manufacturers' use. Connect pin to logic 1 under normal operation. Built-In Self Test start. Reserved for manufacturers' use. Connect pin to ground under normal operation. Reserved for manufacturers' use When Control Bus monitor is enabled, this pin monitors Internal XRISC Interrupt #0. Otherwise, it is used as Test Data Input for the JTAG interface. If JTAG is not used, a 10k pull-up is required. When Control Bus monitor is enabled, this pin monitors the internal Control Bus IO_Ready. Otherwise, it is used as a Test Clock for the JTAG interface. If JTAG is not used, a 10k pull-up is required. When Control Bus monitor is enabled, this pin monitors internal Control Bus Write Enable. Otherwise, it is used as a Test Mode Select for the JTAG interface; a 10k pull-up is required. When Control Bus monitor is enabled, this pin monitors internal Control Bus Address Latch Enable. Otherwise, it is used as a Test Reset for the JTAG interface; a 10k pull-up is required. When Control Bus monitor is enabled, these pins are connected to the internal Control Bus Address and Data. When CBUS_ALE is 1, the Address on the Control Bus is output. Otherwise, Data on Control Bus is output. 10k pull-down is required. Reserved; 10k pull-down is required. Reserved; 10k pull-down is required. Reserved in functional mode. In JTAG mode, this pin is the Test Data Output for the JTAG interface. Reserved; 10k pull-down is required. Reserved; 10k pull-down is required.
BIST_FAIL BIST_DONE BIST_RESET
205 206 207
Output Output Input
BIST_RUN
208
Input
Debug Pins XP_INT0/ TDI 15 Output/ Input
CBUS_IORDY/ TCK
16
Output/ Input
CBUS_WE/ TMS
21
Output/ Input
CBUS_ALE/ TRST
22
Output/ Input
CBUS_AD15CBUS_AD0
23-27, 30-31, 165-173
Output
DEBUG_MODE DBG_INT SYNC_HPI RET_INT/TDO
204 198 197 18
Input Input Input Output
INT_ACK/ MON_EN BOOT_SEL
17 12
Input Input
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SDRAM Pins SDRAM_DQ31SDRAM_DQ0 90-93, 96, 97, 100, 103-106, 109, 110, 113, 116, 117, 57, 62-65, 68-70, 45, 48-51, 54-56 123, 77-79, 82-84, 87, 118, 119, 122 126, 129 130 131 132 135 136 71 76 Input/ Output SDRAM Data
SDRAM_A10SDRAM_A0 SDRAM_BA1SDRAM_BA0 SDRAM_CS# SDRAM_RAS# SDRAM_CAS# SDRAM_WE# SDRAM_DQM SDRAM_CLK SDRAM_CLK_LB
Output
SDRAM Address
Output Output Output Output Output Output Output Input
SDRAM Bank Address SDRAM Chip Select SDRAM Row Address Select SDRAM Column Address Select SDRAM Write Enable SDRAM DQ Mask SDRAM Clock. Connect this pin to the SDRAM chip clock input pin. SDRAM Clock Loop Back. This pin is used to compensate transfer delays on SDRAM signals. Connect this pin to the SDRAM chip clock input pin via a separate route from the SDRAM_CLK connection. See the SDRAM clock scheme in Error! Reference source not found..
Video Data Input Pins PDATA0-PDATA7 HREF 146-149, 152-155 156 Input Input Pixel Data Input Horizontal Reference. Active edge on this pin indicates beginning of active video data in a horizontal period. The active edge can be configured as a positive or negative edge. Vertical Reference. Active edge on this pin indicates beginning of active video data in a vertical period. The active edge can be configured as a positive or negative edge. Pixel Clock
VREF
157
Input
PCLK
158
Input
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HPI Pins AD0-AD15 161-162, 34-42, 178-182 186 185 184 183 143 142 145 144 141 140 139 Input/ Output Output Input Input Input Input/ Output Input/ Output Input Supply Supply Output Input HPI Address and Data multiplexed bus.
INT ALE RD# WR# USB Pins USB DATAUSB DATA+ USB_CLK VDD_USB VSS_USB SUSPEND SUSPEND_LB
HPI Interrupt request to external host. HPI Address Latch Enable HPI Read strobe (active low) HPI Write strobe (active low) USB DataUSB Data+ 48MHz USB Clock input. Use as USB clock input when USB clock PLL is bypassed. VDD for USB; connect to 3.3V power supply. VSS for USB; connect to ground. USB Suspend output. This pin is high when GO7007 goes into suspend mode. USB Suspend Loop Back. Usually connected to SUSPEND via R-C network for a delayed start of internal clock when GO7007 resumes from suspend state. USB/HPI Select input. Tying pin to VDD will enable USB functionality and disable HPI interface. To use only HPI interface, tie pin to VSS. Pin status will be sampled only upon power-on reset. USB Reset Enable. Tie pin to logic 1 for USB bus to reset other parts of GO7007. To disable this feature, connect pin to ground. Changing the status of this pin after power-on will have no effect. General Purpose I/O pins programmed as input or output on a pin-by-pin basis. Global Reset input. Setting pin low (at least 100s) will reset GO7007 (active low).
USB_EN
7
Input
USBRST_EN
200
Input
GPIO Pins GPIO3-GPIO0 192, 191, 188, 187 201 Input/ Output Input
Reset and Power Supply Pins RESET#
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VDD_CORE
202, 189, 176, 163, 150, 137, 124, 111, 98, 85, 72, 59, 46, 32, 19 194, 175, 160, 134, 128, 121, 115, 108, 102, 95, 89, 81, 75, 67, 61, 53, 44, 28, 13 203, 190, 177, 164, 151, 138, 125, 112, 99, 86, 73, 60, 47, 33, 20 193, 174, 159, 133, 127, 120, 114, 107, 101, 94, 88, 80, 74, 66, 58, 52, 43, 29, 14
Supply
1.8V power supply for Core logic.
VDD_IO
Supply
3.3V power supply for IO
VSS_CORE
Supply
Ground for Core logic
VSS_IO
Supply
Ground for IO
__________________________
About WIS WIS Technologies is a privately held, fabless semiconductor company. At WIS Technologies, an international team of experts in image processing and digital communication create innovative chip technology and software. WIS provides advanced features and unprecedented levels of integration, performance and quality, enabling complete, scalable, and highly configurable multimedia communication systems. WIS Technologies Headquarters 697 River Oaks Parkway San Jose, CA 95134-1907 t | 408.526.1000 f | 408.526.9214 e | sales@wischip.com www.wischip.com USA * China * Japan * Taiwan (c)2003 WIS Technologies, Inc. All Rights Reserved. The WIS logo and the WIS family of product names are trademarks of WIS Technologies, Inc. All other trademarks mentioned herein are properties of their respective holders. All information in this document is subject to change without notice. The information contained in this document was obtained in specific environments and is considered an example. Results may vary in different operating environments. Under no circumstances will WIS Technologies be liable for damages resulting from the information contained in PD03.120-2 this document.
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